On chip embedded memory with non-volatility can enable energy and computational efficiency. Several new types of solid-state, high-density, non-volatile memories store information using a memory element with a variable resistance. The resistance of spin transfer torque—magnetic random access memory (STT-MRAM) depends on the relative magnetization polarities of two magnetic layers. Other variable resistance memories include resistive RAM (ReRAM) and conductive bridging RAM (CbRAM), whose resistances depend on the formation and elimination of conduction paths through a dielectric or an electrolyte. There is also phase change memory (PCM), for which the resistivity of a cell depends on the crystalline or amorphous state of a chalcogenide.
FIG. 1 illustrates a two terminal 1T-1MTJ (Magnetic Tunnel Junction) bit-cell 100 for STT-MRAM. Bit-cell 100 includes an access transistor M1 and an MTJ device. The MTJ device is the storage element of STT-MRAM, which includes a pinned magnetic layer and a free magnetic layer. The free magnetic layer magnetization orientation can change with the write current direction. If the write current flows from the free magnetic layer to the pinned magnetic layer, the free magnetic layer magnetization aligns with the pinned magnetic layer and the MTJ device is in the parallel state (RP) with low resistance. If the write current flows from the pinned magnetic layer to the free magnetic layer, the free magnetic layer magnetization direction opposes the pinned magnetic layer and the MTJ device is in the anti-parallel (RAP) state with high resistance.
For these resistive memories, read operation is generally faster than write operation, and the write current is generally larger than the read current. Unlike SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory), which consume transient write power, resistive memory still consumes static write power whether or not the cell is flipped during write operation. The read power of these resistive memories may also be static depending on the implementation of the read sensor. Reducing read and write energies are a challenge for resistive memory in order to meet the targets for high performance and low power applications.